1. Field of the Invention
The present disclosure generally relates to the fabrication of integrated circuits, and, more particularly, to the contact level of a semiconductor device, in which contact areas, such as drain and source regions, as well as gate electrode structures, are connected to the metallization system of the semiconductor device.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very high number of circuit elements, especially transistors, are provided and operated on a restricted chip area. Although immense progress has been made over recent decades with respect to increased performance and reduced feature sizes of the circuit elements, the ongoing demand for enhanced functionality of electronic devices forces semiconductor manufacturers to steadily reduce the dimensions of the circuit elements and to increase the operating speed thereof. The continuing scaling of feature sizes, however, involves great efforts in redesigning process techniques and developing new process strategies and tools so as to comply with new design rules. Generally, in complex circuitry including complex logic portions, MOS technology is presently a preferred manufacturing technique in view of device performance and/or power consumption and/or cost efficiency. In integrated circuits including logic portions fabricated by MOS technology, field effect transistors (FETs) are provided that are typically operated in a switched mode, that is, these devices exhibit a highly conductive state (on-state) and a high impedance state (off-state). The state of the field effect transistor is controlled by a gate electrode, which controls, upon application of an appropriate control voltage, the conductivity of a channel region formed between a drain region and a source region.
On the basis of the field effect transistors, more complex circuit components may be composed, such as inverters and the like, thereby forming complex logic circuitry, embedded memories and the like. Due to the reduced dimensions, the operating speed of the circuit components has been increased with every new device generation, wherein, however, the limiting factor of the finally achieved operating speed of complex integrated circuits is no longer the individual transistor element but the electrical performance of the complex wiring system, which may be formed above the device level including the actual semiconductor-based circuit elements, such as transistors and the like. Typically, due to the large number of circuit elements and the required complex layout of modern integrated circuits, the electrical connections of the individual circuit elements cannot be established within the same device level on which the circuit elements are manufactured, but require one or more additional metallization layers, which generally include metal-containing lines providing the inner-level electrical connection, and also include a plurality of inter-level connections or vertical connections, which are also referred to as vias. These vertical interconnect structures comprise an appropriate metal and provide the electrical connection of the various stacked metallization layers.
Furthermore, in order to actually connect the circuit elements formed in the semiconductor material with the metallization layers, an appropriate vertical contact structure is provided, which connects, with one end, to a respective contact region of a circuit element, such as a gate electrode and/or the drain and source regions of transistors, and, with another end, to a respective metal line in the metallization layer and/or to a contact region of a further semiconductor-based circuit element, in which case the interconnect structure in the contact level is also referred to as a local interconnect. The contact structure may comprise contact elements or contact plugs having a generally square-like or round shape that are formed in an interlayer dielectric material, which in turn encloses and passivates the circuit elements. Upon further shrinkage of the critical dimensions of the circuit elements in the device level, the dimensions of metal lines, vias and contact elements also have to be adapted to the reduced dimensions, thereby requiring sophisticated metal-containing materials and dielectric materials in order to reduce the parasitic capacitance in the metallization layers and provide a sufficiently high conductivity of the individual metal lines and vias. For example, in complex metallization systems, copper in combination with low-k dielectric materials, which are to be understood as dielectric materials having a dielectric constant of approximately 3.0 or less, are typically used in order to achieve the required electrical performance and the electro-migration behavior as is required in view of reliability of the integrated circuits. Consequently, in lower-lying metallization levels, metal lines and vias having critical dimensions of approximately 100 nm and significantly less may have to be provided in order to achieve the required “packing density” in accordance with density of circuit elements in the device level.
Upon further reducing the dimensions of the circuit elements, for instance using critical dimensions of 50 nm and less, the contact elements in the contact level have to be provided with critical dimensions in the same order of magnitude. The contact elements typically represent plugs, which are formed of an appropriate metal or metal composition, wherein, in sophisticated semiconductor devices, tungsten in combination with appropriate barrier materials has proven to be a viable contact metal. When forming tungsten-based contact elements, typically the interlayer dielectric material is formed first and is patterned so as to receive contact openings, which extend through the interlayer dielectric material to the corresponding contact areas of the circuit elements. In particular, in densely packed device regions, the lateral size of the drain and source areas and thus the available area for the contact regions is 100 nm and significantly less, thereby requiring extremely complex lithography and etch techniques in order to form the contact openings with well-defined lateral dimensions and with a high degree of alignment accuracy.
For this reason, contact technologies have been developed in which contact openings are formed in a self-aligned manner by removing dielectric material, such as silicon dioxide, selectively from the spaces between closely spaced gate electrode structures. That is, after completing the transistor structure, the gate electrode structures are used as etch masks for selectively removing the silicon dioxide material in order to expose the contact regions of the transistors, thereby providing self-aligned trenches which are substantially laterally delineated by the spacer structures of the gate electrode structures. Consequently, a corresponding lithography process only needs to define a global contact opening above an active region, wherein the contact trenches then result from the selective etch process using the gate electrode structures, i.e., the portions exposed by the global contact opening, as an etch mask. Thereafter, an appropriate contact material, such as tungsten and the like, may be filled into the contact trenches.
Moreover, generally, a reduction of length of the channel regions is associated with the requirement of an increase of the capacitive coupling between the gate electrode and the channel region, in particular in high performance transistors, and for this reason typically the gate dielectric material separating the channel region from an electrode material of the gate electrode structures is reduced in thickness. In the past, silicon dioxide-based gate dielectric materials have been used due to the superior characteristics of a silicon/silicon dioxide interface with respect to high temperature treatments and the like, wherein, however, upon continuously shrinking the critical dimensions of the transistors, the moderately low dielectric constant of silicon dioxide-based dielectric materials may require a thickness of 2 nm and less of a corresponding gate insulation layer in order to comply with the performance requirements of transistors having a gate length well below 80 nm. In this case, however, the resulting leakage currents caused by hot carrier injection and direct tunneling of charge carriers through the extremely thin silicon dioxide-based gate dielectric may no longer be compatible with thermal design power requirements. Therefore, new strategies have been developed in which at least a significant portion of the conventional gate dielectric material is replaced by a dielectric material of increased dielectric constant, wherein any such materials are typically referred to as high-k dielectric materials and have a dielectric constant of 10.0 and higher. For example, a plurality of metal oxides and silicates, such as hafnium oxide, zirconium oxide and the like, may be efficiently used as high-k dielectric materials. It turns out, however, that the incorporation of the high-k dielectric material also requires appropriately adapted strategies for adjusting the work function values of the gate electrode structures, which in turn requires the incorporation of specific work function metal species, such as titanium, tantalum, aluminum, lanthanum and the like, which may also be used as efficient electrode metals, thereby also increasing electrical conductivity and reducing generation of any depletion zones in the vicinity of the gate dielectric material, as is also typically encountered in conventional silicon dioxide/polysilicon gate electrode structures. Since the high-k dielectric materials and the work function metal species may be highly sensitive with respect to high temperature treatments and the exposure to critical process atmospheres, as are typically encountered during the entire manufacturing process, in some very promising approaches these materials are provided in a very late manufacturing stage on the basis of a so-called replacement gate approach.
In sophisticated process strategies, the replacement gate approach is typically combined with a self-aligned formation of the contact elements, as discussed above, wherein the contact elements are formed prior to applying the replacement gate approach in order to provide a fully encapsulated replacement gate electrode structure for enabling the application of a selective etch strategy, as described above. In this case, however, the further processing, i.e., applying the replacement gate approach, may be significantly affected by the presence of the metal in the contact elements, as will be described in more detail with reference to FIG. 1.
FIG. 1 schematically illustrates a cross-sectional view of a semiconductor device 100 in a very advanced manufacturing stage. As illustrated, the device 100 comprises a substrate 101, such as a silicon substrate or any other appropriate carrier material, above which is formed a semiconductor layer 102, such as a silicon layer and the like. The semiconductor layer 102 is laterally divided into a plurality of semiconductor regions or active regions, wherein, for convenience, a single active region 102a is illustrated in FIG. 1. Generally, an active region is to be understood as a semiconductor region in the layer 102, in and above which one or more transistors are to be formed. The active region 102a is laterally delineated by an isolation region 102c, which is typically provided in the form of a shallow trench isolation (STI). Moreover, in the manufacturing stage shown, a plurality of transistors, such as P-channel transistors or N-channel transistors, are formed in and above the active region 102a and comprise corresponding drain and source regions 151, which may have any appropriate lateral and vertical profile in accordance with the overall process and device requirements. For example, the drain and source regions 151 may be comprised of dopant species incorporated by implantation techniques, selective epitaxial growth techniques and the like. Furthermore, in some cases, a strain-inducing semiconductor alloy, such as a silicon/germanium material, a silicon/tin material, a silicon/carbon material and the like, may be incorporated in at least a portion of the drain and source regions 151 so as to induce a desired type of strain in a channel region 153 of the transistors. Furthermore, each of the transistors comprises a gate electrode structure 160 which, in the manufacturing stage shown, is to be understood as a replacement gate electrode structure since significant portions thereof are to be replaced by appropriate gate materials in a later manufacturing stage. The gate electrode structures may comprise a dielectric material or etch stop material 162, such as silicon dioxide and the like, followed by a placeholder material 161, which is typically provided in the form of a polysilicon material, which in turn is covered by a dielectric cap layer or layer system 164, for instance provided in the form of a silicon nitride material. Furthermore, a sidewall spacer structure 163, which may be comprised of several spacer elements and the like, is provided so as to confine the material 161 at sidewalls thereof. For example, the spacer structure 163 typically comprises at least one spacer element formed of silicon nitride. The gate electrode structures 160 may have a gate length, i.e., in FIG. 1, the horizontal extension of the placeholder material 161, of 50 nm and significantly less, such as 30 nm, so that a spacing, indicated as 122a, between adjacent gate electrode structures 160 may be on the order of magnitude of 100 nm and significantly less. Consequently, implementing a self-aligned manufacturing strategy for forming contact elements so as to connect to contact regions of the transistors, i.e., to a portion of the drain and source regions 151, may thus provide significant enhancement with respect to process robustness and reliability of the resulting contact elements, as discussed above.
Furthermore, in this manufacturing stage, an interlayer dielectric material 121, such as a silicon dioxide material, is provided above the semiconductor layer 102 and has formed therein an appropriate “global” contact opening 121a, which thus defines the lateral size and position above the active region 102a in which the contact regions of the drain and source regions 151 are exposed.
The semiconductor device 100 as shown in FIG. 1 may be formed on the basis of any appropriate process strategy. For example, the isolation region 102c is formed in the semiconductor layer 102 by applying well-established lithography, etch, deposition, anneal and polishing techniques, thereby laterally delineating the active region 102a. Prior to or after providing the isolation region 102c, any appropriate well dopant species may be incorporated, for instance by ion implantation, followed by anneal processes and the like. Next, appropriate materials for the gate electrode structures 160 are formed, for instance by deposition and the like, followed by any appropriate complex patterning regime so as to pattern the materials 161, 162 and 164 with the desired lateral dimensions in accordance with the overall design rules. Thereafter, any further processes may be applied so as to complete the transistor structures, which may include the incorporation of strain-inducing materials (not shown), the introduction of dopant species for the drain and source regions 151, the provision of the spacer structure 163 and the like, which may be accomplished by applying any appropriate process strategy. Consequently, in this manufacturing stage, the placeholder material 161 is reliably encapsulated by the cap layer 164 and the spacer structure 163. In some cases, appropriate contact regions may be formed, for instance, by incorporating a metal silicide in the drain and source regions 151, while, in other cases, a corresponding metal silicide may be provided in a later manufacturing stage. Next, the interlayer dielectric material 121 may be deposited, for instance by applying any appropriate deposition technique, such as spin-on techniques, in combination with subsequent treatments in the form of anneal processes and the like so as to provide the material 121 with desired characteristics. For example, silicon dioxide material, possibly in combination with an etch stop layer, such as silicon nitride (not shown), may be provided laterally adjacent and above the gate electrode structures 160. If required, a planarization process may be applied, while in other cases an appropriate lithography process is performed in order to provide an etch mask that defines the lateral size and position of the opening 121a. Thereafter, a selective etch process is applied, for instance by using well-established plasma assisted etch recipes, in order to remove an exposed portion of the material 121, while the cap layer 164 and the spacer structure 163, possibly in combination with an additional etch stop layer, may act as etch masks and etch stop materials, respectively. Thereafter, any residual materials, such as etch stop materials, may be removed by using any appropriate etch or cleaning recipe while still reliably preserving the materials 164 and 163. Next, any appropriate contact materials, such as titanium nitride in combination with tungsten, may be deposited, thereby reliably filling the spaces 122a which now act as contact openings, thereby forming corresponding contact elements in a self-aligned manner. Thereafter, any excess material may be removed, for instance by using a chemical mechanical polishing (CMP) process, wherein, in a final phase, the tungsten material in the contact openings 121a and the dielectric cap material 164 in combination with the interlayer dielectric material 121 is to be removed, wherein preferably a very similar removal rate for the three different materials is to be accomplished in order to avoid undue recessing or dishing of the contact metal, while nevertheless reliably exposing the placeholder material 161 in the gate electrode structures 160. It should be appreciated that a corresponding polishing recipe is very difficult to establish and thus significant process non-uniformities may typically be associated with the corresponding planarization process. In other cases, any additional etch and cleaning processes may be required, which in turn, however, may have a significant influence on the previously formed contact metal.
After the exposure of the placeholder polysilicon material 161, corresponding selective etch recipes have to be applied in order to reliably remove the material 161, while, however, also avoiding undue material erosion in the contact elements formed in the openings 121a. After the removal of the polysilicon material 161 and possibly of the material 162, efficient cleaning recipes, for instance for removing residual oxide materials, may have to be applied, wherein, however, well-established and highly efficient cleaning agents, such as APM/SPM (ammonium hydrogen peroxide mixture/sulfuric acid hydrogen peroxide mixture) may not be available since these agents also “efficiently” remove tungsten, thereby significantly damaging the contact elements. Furthermore, during the subsequent processing, i.e., the deposition of the different work function metals and the patterning thereof, a high probability may exist for damaging the contact elements so that, generally, significant yield loss is observed when forming self-aligned contact elements in the context of sophisticated replacement gate approaches.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.